Integrated Circuits (ICs) typically comprise a memory for data storage comprising multiple memory cells, such as Static Random Access Memory (SRAM) cells. Various techniques have been suggested for estimating the speed of memory cells. For example, U.S. Pat. No. 9,123,446, whose disclosure is incorporated herein by reference, describes an IC that includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells. The memory cell design is modified at lower layers of the memory cell, independent of the memory cell port interface, to enable a dedicated coupling of the modified memory cells defining inversion stages of the ring oscillator. The speed determination circuit is configured to determine a speed of the ring oscillator.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.